Workshop on Fault-Tolerant Quantum Computer System Architecture

Thank you very much for attending and fruitful discussions!

Thanks to everyone’s contribution, we were able to have a meaningful discussion with many participants. I am confident that interdisciplinary discussions will bear fruit in the realization of FTQC. We plan to provide further opportunities to exchange research results in the future. We thank everyone for their cooperation.

About FTQCSA

The pursuit of Fault-Tolerant Quantum Computer (FTQC) represents a promising direction in enhancing computation capability, with far-reaching implications for various fields. However, the research and development of FTQC necessitate a multidisciplinary approach, drawing on expertise from diverse areas, including quantum coding theory, quantum processing unit design, electronics engineering for quantum-classical interfaces, quantum networks, computer architecture, compilation techniques, and FTQC integration with high-performance computing. As we embark on the path to achieving quantum advantage through FTQC, it is clear that sustained efforts are required to scale up FTQC systems while reducing the resources needed to operate them.

The journey toward harnessing the power of FTQC has just begun, and it is essential to recognize that long-term commitment and collaboration are crucial for overcoming the complex challenges ahead. In this context, the motivation behind this workshop lies in the need to foster international cooperation among researchers from diverse disciplines. The primary objective of this workshop is to provide a platform where experts can converge to share their latest advancements, discuss system-level challenges, and collaborate on strategies to accelerate the development of FTQC systems. By facilitating an exchange of ideas and expertise, we aim to drive progress toward realizing quantum advantages.

Date and Venue

• Date: June 22, 2025 in conjunction with ISCA2025
• Venue: Komatsu Hall (B1F), Research Innovation Center (Bld. 121) , Waseda University
  (513 Wasedatsurumaki-cho, Shinjuku-ku, Tokyo, 162-0041, JAPAN)

Call for Abstracts

• Please refer to this page.

Call for Posters

• Please fill and submit the form here.
  The deadline is tentatively May 28th.

Presentations

Invited speakers

• VAN METER, Rodney D.
  Professor, Faculty of Environment and Information Studies, Graduate School of Media and Governance, Keio University
• Yoshiyasu Doi
  Senior Research Director, Quantum Laboratory, Fujitsu Research, Fujitsu Limited

Accepted talks

• Koki Aoyama, Masao Okita, Takafumi Tomita, and Fumihiko Ino,
  “Square-Root Time Plan for Defect-Free Atom Array Reconfiguration with Lattice-shaped Mobile Tweezers”
• Junichi Haruna and Keisuke Fujii,
  “Hierarchical Quantum Error Correction with Hypergraph Product Code and Rotated Surface Code”
• Yutaka Hirano and Keisuke Fujii,
  “Locality-aware Pauli-based computation for local magic state preparation”
• Kohdai Kuroiwa and Yuya O. Nakagawa,
  “Averaging gate approximation error and performance of Unitary Coupled Cluster ansatz in Pre-FTQC Era”
• Yugo Takada and Hayata Yamasaki,
  “Doubly-polylog-time-overhead fault-tolerant quantum computation by a polylog-time parallel minimum-weight perfect matching decoder”
• Joshua Viszlai, Margaret R. Martonosi, and Frederic T. Chong,
  “Decoding the Performance Gap: Propagation-Aware Compilation of Stabilizer Circuits”

Posters

• Yutaka Hirano, Keisuke Fujii,
  “Locality-aware Pauli-based computation for local magic state preparation”
• Tomohiro Itogawa, Yugo Takada, Yutaka Hirano, Yutaro Akahoshi, Keisuke Fujii,
  “Efficient Magic State Distillation by Zero-level Distillation”
• Hiroaki Murakami, Kenzo Makino, Yasunori Lee, Keita Kanno, Tomonori Fukuta,
  “Resource Estimation for Matrix Inversion via QSVT with the Clifford+T Gate Set”
• Theerapat Tansuwannont, Yugo Takada, Keisuke Fujii,
  “Clifford gates with logical transversality for self-dual CSS codes”
• Joshua Viszlai, Margaret R. Martonosi, Frederic T. Chong,
  “Decoding the Performance Gap: Propagation-Aware Compilation of Stabilizer Circuits”

Registration

• Please register to participate from the ISCA website.
• Note that presenters are also required to register.
• Early registration is available until May 22.

Detailed program

• Please refer to this page.

Committees

Organizing Committee

• Chair: Teruo Tanimoto, Kyushu University, Japan
• Vice Chair: Yosuke Ueno, RIKEN, Japan
• Program Committee Chair: Yasunari Suzuki, NTT/RIKEN, Japan
• Program Committee Vice Chair: Shota Nagayama, Keio University/Mercari, Japan

Program Committee

• Ilkwon Byun (Kyushu University)
• Yufei Ding (University of California, San Diego)
• Poulami Das (University of Texas at Austin)
• Akihito Soeda (National Institute of Informatics, Japan)
• Gokul Subramanian Ravi (University of Michigan)
• Swamit Tannu (University of Wisconsin-Madison)
• Hayata Yamasaki (The University of Tokyo)

Contact

• Email: ftqcsa-oc at googlegroups.com